TI TPS51206DSQR

转换器，DDR3.1V ~ 6.5V0.5V ~ 0.9V

Overview

APPLICATIONS ·DDR2/DDR3/DDR3L Memory Power Supplies ·SSTL_18,SSTL_15,SSTL_135 and HSTL Termination DESCRIPTION The TPS51206 is a sink/source double date rate (DDR) termination regulator with VTTREF buffered reference output. It is specifically designed for low input voltage, low cost, low external component count systems where space is a key consideration. The TPS51206 maintains fast transient response and only requires 1× 10-uF of ceramic output capacitance. The TPS51206 supports a remote sensing function and all power requirements for DDR2, DDR3 and Low-Power DDR3 (DDR3L) VTT bus. The VTT current capability is ±2A peak. The TPS51206 supports all of the DDR power states, putting VTT to High-Z in S3 state(suspend to RAM) and discharging VTT and VTTREF in S4/S5 state(suspend to disk). The TPS51206 is available in 10-pin,2×2, SON (DSQ) PowerPADTM package and specified from-40℃ to 85℃.

Features

Tape & Reel (TR) Package
Converter, DDR Applications
3.1V ~ 6.5V Voltage - Input
1 Number of Outputs
0.5V ~ 0.9V Voltage - Output
Surface Mount Mounting Type