TI TPS51200DRCR

转换器，DDR2.38V ~ 3.5V

Overview

Designed specifically for bus termination in DDR and QDR memory applications. These sink/source tracking termination regulators are aimed for space saving, low-cost applications with low external part counts.

Features

• Input Voltage: Supports 2.5-V Rail and 3.3-V Rail

• VLDOIN Voltage Range: 1.1 V to 3.5 V

• Sink and Source Termination Regulator Includes Droop Compensation

• Requires Minimum Output Capacitance of 20-μF (Typically 3 × 10-μF MLCCs) for Memory Termination Applications (DDR)

• PGOOD to Monitor Output Regulation

• EN Input

• REFIN Input Allows for Flexible Input Tracking Either Directly or Through Resistor Divider

• Remote Sensing (VOSNS)

• ±10-mA Buffered Reference (REFOUT)

• Built-in Soft Start, UVLO, and OCL

• Thermal Shutdown

• Supports DDR, DDR2, DDR3, DDR3L, Low Power DDR3, and DDR4 VTT Applications

• 10-Pin VSON Package With Thermal Pad

Applications

• Memory Termination Regulator for DDR, DDR2,

• DDR3, DDR3L, Low-Power DDR3, and DDR4

• Notebooks, Desktops, and Servers

• Telecom and Datacom

• Copiers and Printers

• Set-Top Boxes

• Base Stations

• LCD-TVs and PDP-TVs