TI CDCVF2505DR

PLL 时钟驱动器带旁路LVTTLLVTTL

Overview

The CDCVF2505DR is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. This device uses a PLL to precisely align the output clocks (1Y[0-3] and CLKOUT) to the input clock signal (CLKIN) in both frequency and phase. The CDCVF2505DR operates at 3.3 V and also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

Because it is based on the PLL circuitry, the CDCVF2505DR requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN, and following any changes to the PLL reference.

Features

Tape & Reel (TR) Package
Available in the 8-SOIC (0.154, 3.90mm Width)
Supply voltage of 3.3V
Operating supply voltage of 3.3V
Load capacitance of 25pF

Surface Mount Mounting Type

Applications

There are a lot of Texas Instruments
CDCVF2505DR Clock Generators applications.

• 1 Gigabit Ethernet
• 10 Gigabit Ethernet
• FPGA and processor clocks
• Line cards used in telephone exchange
• Fiber Channel
• PCI express cards
• Infotainment systems
• Medical equipment
• Multi-function printers
• Media broadcast servers