TI CDCUA877NMKR

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Overview

The CDCUA877ZQL is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input pair (CK, CK) to ten differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks (FBIN, FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD). When OE is low, the clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS (output select) is a program pin that must be tied to GND or VDD. When OS is high, OE functions as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running. When AVDD is grounded, the PLL is turned off and bypassed for test purposes.

The CDCUA877ZQL is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from -40°C to 85°C).

Features

Tape & Reel (TR) Package
Yes PLL
Memory, DDR2 Main Purpose
Clock Input
Clock Output
1 Number of Circuits
1:10 Ratio - Input:Output
Yes/Yes Differential - Input:Output
410MHz Frequency - Max
1.7V ~ 1.9V Voltage - Supply
Surface Mount Mounting Type