Microchip SY100S838LZC

时钟发生器无ECL，PECL时钟

Overview

The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. In addition, by using the VBB output, a sinusoidal source can be ACcoupled into the device. If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the input of the SY100S838/L under singleended input conditions. As a result, this pin can only source/sink up to 0.5mA of current.

■ Available in 20-pin SOIC package

Features

Precision Edge® Series
Available in the 20-SOIC (0.295, 7.50mm Width)

Surface Mount Mounting Type

Applications

There are a lot of Microchip Technology
SY100S838LZC Clock Generators applications.

• Sampling clocks for ADC and DAC
• 1 Gigabit Ethernet
• 10 Gigabit Ethernet
• FPGA and processor clocks
• Line cards used in telephone exchange
• Fiber Channel
• PCI express cards
• Infotainment systems
• Medical equipment
• Multi-function printers