ON FDG6320C_D87Z

MOSFET（金属氧化物）逻辑电平门N 和 P 沟道25V220mA，140mA4 欧姆 @ 220mA，4.5V1.5V @ 250µA

Overview

These dual N & P-Channel logic level enhancement mode field effect transistors are produced using a proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETS. Since bias resistors are not required, this dual digital FET can replace several different digital transistors, with different bias resistor values.

Features

Tape & Reel (TR) Package
MOSFET (Metal Oxide) Technology
Logic Level Gate FET Feature
25V Drain to Source Voltage (Vdss)
220mA, 140mA Current - Continuous Drain (Id) @ 25°C
4Ohm @ 220mA, 4.5V Rds On (Max) @ Id, Vgs
1.5V @ 250µA Vgs(th) (Max) @ Id
0.4nC @ 4.5V Gate Charge (Qg) (Max) @ Vgs
9.5pF @ 10V Input Capacitance (Ciss) (Max) @ Vds
300mW Power - Max
Surface Mount Mounting Type