NXP LPC55S69JBD100K

ARM® Cortex®-M33150MHz640KB（640K x 8）

Overview

The LPC55S69JBD100K MCU family builds on the world’s first general-purpose Cortex-M33 based microcontroller introduced with the LPC5500 series. This high-efficiency family leverages the new Armv8-M architecture to introduce new levels of performance and advanced security capabilities including TrustZone-M and co-processor extensions. The LPC55S69JBD100K family enables these co-processors extensions and leverages them to bring significant signal processing efficiency gains from a proprietary DSP accelerator offering a 10x clock cycle reduction. An optional second Cortex-M33 core offers flexibility to balance high performance and power efficiency.

In addition, the LPC55S69JBD100K MCU family provides benefits from 40nm NVM based process technology cost advantages, broad scalable packages, and memory options, as well as a robust enablement including MCUXpresso Software and Tools ecosystem and low-cost development boards.

Features

• CASPER Crypto co-processor is provided to enable hardware acceleration for various, functions required for certain asymmetric cryptographic algorithms, such as Elliptic

• Curve Cryptography (ECC).

• PowerQuad hardware accelerator for (fixed and floating point unit) CMSIS DSP functions with the support of SDK software API faster execution of ARM CMSIS instruction set.

• On-chip memory:

-Up to 640 KB on-chip flash program memory with flash accelerator and 512-byte page erase and write.

-Up to 320 KB total SRAM consisting of 32 KB SRAM on Code Bus, 272 KB SRAM on System Bus (272 KB is contiguous), and an additional 16 KB USB SRAM on

• System Bus which can be used by the USB interface or for general purpose use. 

• PRINCE module for real-time encryption of data being written to on-chip flash and decryption of encrypted flash data during reading to allow asset protection, such as securing application code, and enabling the secure flash update.

Applications

• Embedded applications