ON MC100EPT21DTR2G

混合信号

Overview

The MC100EPT21DTR2G is a 3.3V differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator in 8 pin TSSOP package. Because LVPECL (positive ECL), LVDS, positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small outline 8 lead SOIC package makes MC100EPT21DTR2G ideal for applications which require the translation of a clock or data signal. The VBB output allows this device to be cap coupled in either single ended or differential input mode. VBB output is tied to D input and D is driven for a non inverting buffer or VBB output is tied to the D input and D is driven for an inverting buffer when single ended cap coupled. VBB output is connected through a resistor to each input pin when cap coupled differentially. If used the VBB pin should be bypassed to VCC via a 0.01µF capacitor. It is used in precision clock translation applications.

Features

100EPT Series
8-TSSOP, 8-MSOP (0.118, 3.00mm Width) package
8 pin count
100EPT series
8 pins

Surface Mount Mounting Type

Applications

There are a lot of ON Semiconductor
MC100EPT21DTR2G voltage translators & level shifters applications.

• MDIO
• PMBus
• SMBus
• SDIO
• UART
• I2C
• Automotive
• Personal computing
• Automotive infotainment
• Advanced Driver Assistance System (ADAS)