NXP PCA9517D,118

缓冲器，转接驱动器2 线式总线2 线式总线400kHz2

Overview

The PCA9517D,118 is a CMOS integrated circuit that provides level shifting between low voltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) I²C-bus or SMBus applications. While retaining all the operating modes and features of the I²C-bus system during the level shifts, it also permits extension of the I²C-bus by providing bidirectional buffering for both the data (SDA) and the clock (SCL) lines, thus enabling two buses of 400 pF. Using the PCA9517D,118 enables the system designer to isolate two halves of a bus for both voltage and capacitance. The SDA and SCL pins are over voltage tolerant and are high-impedance when the PCA9517D,118 is unpowered.

The output pull-down on the B-side internal buffer LOW is set for approximately 0.5 V, while the input threshold of the internal buffer is set about 70 mV lower (0.43 V). When the B-side I/O is driven LOW internally, the LOW is not recognized as a LOW by the input. This prevents a lock-up condition from occurring. The output pull-down on the A-side drives a hard LOW and the input level is set at 0.3VCCA to accommodate the need for a lower LOW level in systems where the low voltage side supply voltage is as low as 0.9 V.

Features

Tape & Reel (TR) Package
Buffer, ReDriver Type
I²C Applications
400kHz Data Rate (Max)
2 Number of Channels
6 pF Capacitance - Input
2.7V ~ 5.5V Voltage - Supply
5mA Current - Supply
Surface Mount Mounting Type