NXP PCA9511ADP,118

缓冲器，加速计2 线式总线2 线式总线400kHz1

Overview

The PCA9511ADP is a hot swappable I²C-bus and SMBus Buffer that allows I/O card insertion into a live backplane without corrupting the data and clock buses. Control circuitry prevents the backplane from being connected to the card until a stop command or bus idle occurs on the backplane without bus contention on the card. When the connection is made, this provides bidirectional buffering, keeping the backplane and card capacitances isolated. Its rise time accelerator circuitry allows the use of weaker DC pull-up currents while still meeting rise time requirements. It incorporates a digital ENABLE input pin, which enables the device when asserted HIGH and forces the device into a low current mode when asserted LOW and an open-drain READY output pin, which indicates that the backplane and card sides are connected together or not. During insertion, buffer SDA and SCL lines are pre-charged to 1V to minimize the current required to charge the parasitic capacitance of the chip.

Features

Bulk Package
Buffer, Accelerator Type
400kHz Data Rate (Max)
1 Number of Channels
70ns Delay Time
5 pF Capacitance - Input
2.7V ~ 5.5V Voltage - Supply
3.5mA Current - Supply