NXP MC68LC060RC50

6806050MHz0°C ~ 70°C（TA）

Features

1.6–1.7 Times the MC68040 Performance at the Same Clock Rate with Existing Compliers. 3.2–3.4 Times the Performance of a 25 MHZ MC68040.

Harvard Architecture with Independent, Decoupled Fetch, and Execution Pipelines.

Branch Prediction Logic with a 256-Entry, 4-Way Set-Associative, Virtual-Mapped Branch Cache for Improved Branch Instruction Performance.

A Superscalar Pipeline and Dual Integer Execution Units Achieving Simultaneous, but not Out-of-Order Instruction Execution.

An IEEE Standard, MC68040- and MC68881-/MC68882-Compatible FPU.

An MC68040-Compatible Paged Memory Management Unit with Dual 64-Entry Address Translation Caches

Dual 8-Kbyte Caches (Instruction Cache and Data Cache)

A Flexible, High-Bandwidth Synchronous Bus Interface

User Object-Code Compatible with All Earlier M68000 Microprocessors 

Applications

Communications equipment 

Datacom module 

Industrial 

Lighting 

Personal electronics 

PC & notebooks