NXP MC68360EM25K

CPU32+25MHzDRAM10Mbps（1）0°C ~ 70°C（TA）

Overview

INTRODUCTION The MC68360EM25K QUad Integrated Communication Controller (QUICC™) is a versatile one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications. It particularly excels in communications activities. The QUICC (pronounced “quick”) can be described as a next-generation MC68302 with higher performance in all areas of device operation, increased flexibility, major extensions in capability, and higher integration. The term "quad" comes from the fact that there are four serial communications controllers (SCCs) on the device; however, there are actually seven serial channels: four SCCs, two serial management controllers (SMCs), and one serial peripheral interface (SPI). Features The following list summarizes the key MC68360EM25K QUICC features: • CPU32+ Processor (4.5 MIPS at 25 MHz) — 32-Bit Version of the CPU32 Core (Fully Compatible with the CPU32) — Background Debug Mode — Byte-Misaligned Addressing • Up to 32-Bit Data Bus (Dynamic Bus Sizing for 8 and 16 Bits) • Up to 32 Address Lines (At Least 28 Always Available) • Complete Static Design (0–25-MHz Operation) • Slave Mode To Disable CPU32+ (Allows Use with External Processors) — Multiple QUICCs Can Share One System Bus (One Master) — MC68040 Companion Mode Allows QUICC To Be an MC68040 Companion Memory (SRAM), Electrically Programmable Read-Only Memory (EPROM), Flash EPROM, etc. — Four CAS lines, Four WE lines, One OE line — Boot Chip Select Available at Reset (Options for 8-, 16-, or 32-Bit Memory) — Special Features for MC68040 Including Burst Mode Support • Four General-Purpose Timers — Superset of MC68302 Timers — Four 16-Bit Timers or Two 32-Bit Timers — Gate Mode Can Enable/Disable Counting • Two Independent DMAs (IDMAs) — Single Address Mode for Fastest Transfers — Buffer Chaining and Auto Buffer Modes — Automatically Performs Efficient Packing — 32-Bit Internal and External Transfers • System Integration Module (SIM60) — Bus Monitor — Double Bus Fault Monitor — Spurious Interrupt Monitor — Software Watchdog — Periodic Interrupt Timer — Low Power Stop Mode — Clock Synthesizer — Breakpoint Logic Provides On-Chip Hardware Breakpoints — External Masters May Use On-Chip Features Such As Chip Selects — On-Chip Bus Arbitration with No Overhead for Internal Masters — IEEE 1149.1 Test Access Port • Interrupts — Seven External IRQ Lines — 12 Port Pins with Interrupt Capability — 16 Internal Interrupt Sources — Programmable Priority Between SCCs — Programmable Highest Priority Request • Communications Processor Module (CPM) — RISC Controller — Many New Commands (e.g., Graceful Stop Transmit, Close RxBD) — 224 Buffer Descriptors — Supports Continuous Mode Transmission and Reception on All Serial Channels • Four SCCs — Ethernet/IEEE 802.3 Optional on SCC1 (Full 10-Mbps Support) (Available only on the MC68EN360) — HDLC/SDLC™ (All Four Channels Supported at 2 Mbps) — HDLC Bus (Implements an HDLC-Based Local Area Network (LAN)) — AppleTalk® — Signaling System #7 — Universal Asynchronous Receiver Transmitter (UART) — Synchronous UART — Binary Synchronous Communication (BISYNC) — Totally Transparent (Bit Streams) — Totally Transparent (Frame Based with Optional Cyclic Redundancy Check (CRC)) — Profibus (RAM Microcode Option) — Asynchronous HDLC (RAM Microcode Option) to Support PPP (Point to Point Protocol) — DDCMP™(RAM Microcode Option) — V.14 (RAM Microcode Option) — X.21 (RAM Microcode Option) • Two SMCs — UART — Transparent — General Circuit Interface (GCI) Controller — Can Be Connected to the Time-Division Multiplexed (TDM) Channels • One SPI — Superset of the MC68302 SCP — Supports Master and Slave Modes — Supports Multimaster Operation on the Same Bus • Time-Slot Assigner • Supports Two TDM Channels — Each TDM Channel Can Be T1, CEPT, PCM Highway, ISDN Basic Rate, ISDN Primary Rate, User Defined — 1- or 8-Bit Resolution — Allows Independent Transmit and Receive Routing, Frame Syncs, Clocking — Allows Dynamic Changes — Can Be internally Connected to Six Serial Channels (Four SCCs and Two SMCs) • Parallel Interface Port

Features

• Two 2 x Arm A53 Safe Clusters

• 2 x 32b DDR3/LPDDR2 at 533 MHz 

• Image Signal Processing

• 2 x APEX2 – Image cognition Processing Open CL

• h.264 Codec and MJPEG decoder

• 3D GPU GC3000 (4 Shader) 

• Classic ASIL B/C capable SoC

• LBIST, MBIST

• Voltage and temperature monitoring

Applications

• Surround View

• Front Cameras

• Rear Cameras

• Sensor Fusion

• Lane Departure

• 360° Surround View

• Facial Recognition

• Optical Flow

• Traffic Count

• Autonomous Farming