NXP 74HC73D,653

127ns @ 6V，50pF2V ~ 6V

Overview

  The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (nR) is asynchronous, when LOW it overrides the clock and data inputs, forcing the nQ output LOW and the nQ output HIGH. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 

2. Features and benefits ■ Low-power dissipation ■ Complies with JEDEC standard no. 7A ■ ESD protection: ■ HBM JESD22-A114F exceeds 2000 V ■ MM JESD22-A115-A exceeds 200 V ■ Multiple package options ■ Specified from 40 C to +80 C and from 40 C to +125 C

Features

74HC Series
Bulk Package
Reset Function
JK Type Type
Complementary Output Type
2 Number of Elements
1 Number of Bits per Element
83 MHz Clock Frequency
27ns @ 6V, 50pF Max Propagation Delay @ V, Max CL
Negative Edge Trigger Type
5.2mA, 5.2mA Current - Output High, Low
2V ~ 6V Voltage - Supply
Surface Mount Mounting Type
4 µA Current - Quiescent (Iq)
3.5 pF Input Capacitance