Renesas 9DB801CFLF

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Overview

The 9DB801C is a DB800 Version 2.0 Yellow Cover part with PCI Express® support. It can be used in PC or embedded systems to provide outputs that have low cycle-to-cycle jitter (50 ps), low output-to-output skew (100 ps), and are PCI Express® gen 1 compliant. The 9DB801C supports a 1 to 8 output configuration, taking a spread or non spread differential HCSL input from a CK410(B) main clock such as 954101 and 932S401, or any other differential HCSL pair. 9DB801C can generate HCSL or LVDS outputs from 50 to 200 MHz in PLL mode or 0 to 400 MHz in bypass mode. There are two de-jittering modes available selectable through the HIGH_BW# input pin, high bandwidth mode provides de-jittering for spread inputs and low bandwidth mode provides extra de-jittering for non-spread inputs. The SRC_STOP#, PD#, and individual OE# real-time input pins provide completely programmable power management control.

Features

8 - 0.7V current-mode differential output pairs

Supports zero delay buffer mode and fanout mode

Bandwidth programming available

Outputs cycle-cycle jitter < 50ps

Outputs skew: 50ps

50 - 200MHz operation

The extended frequency range in bypass mode to 400 MHz

PCI Express Gen I compliant

Real-time PLL lock detects output pin

48-pin SSOP/TSSOP package

Available in RoHS-compliant packaging

Applications

Automotive 

Body electronics & lighting 

Communications equipment 

Wired networking 

Industrial 

Electronic point of sale (EPOS)