Renesas 74HC4060P-E

二进制计数器12 V ~ 6 V

Overview

The 74HC4060PW is a 14-stage ripple-carry binary counter/divider and oscillator IC featuring three terminals for oscillation (RS, RTC, and CTC), ten buffered outputs in parallel (from Q3 through Q9 and Q11 up to Q13), and a dominant asynchronous master reset (MR). The design permits the oscillator to be set up for either RC or crystal-based configurations. Additionally, an external clock pulse can be introduced via the RS input in lieu of the oscillator. For more details about this counter pinout, circuit diagram, etc can check the 74HC4060PW datasheet. It can divide an input clock signal by various factors and provide output signals at multiple division stages.

Available in TSSOP and SO packages

Features

74HC Series
Bulk Package
Binary Counter Logic Type
Up Direction
1 Number of Elements
14 Number of Bits per Element
Asynchronous Reset
95 MHz Count Rate
Negative Edge Trigger Type
2 V ~ 6 V Voltage - Supply