Renesas 54FCT574ATLB

87.2ns @ 50pF4.5V ~ 5.5V

Overview

The 54FCT574ATLB is a low jitter, low-skew, high performance PLL-based zero delay buffer for high speed applications. Based on IDT's proprietary low jitter Phase Locked Loop (PLL) techniques, the device provides four low skew outputs at speeds up to 160 MHz at 3.3 V. When one of the outputs is connected directly to FBIN, the rising edge of each output is aligned with the rising edge of the input clock. External delay elements connected in the feedback loops will cause the outputs to occur before the inputs by the amount of propagation delay of the external element.

Features

Bulk Package
Standard Function
1 Number of Elements
8 Number of Bits per Element
7.2ns @ 50pF Max Propagation Delay @ V, Max CL
Positive Edge Trigger Type
15mA, 48mA Current - Output High, Low
4.5V ~ 5.5V Voltage - Supply
Surface Mount Mounting Type
1 mA Current - Quiescent (Iq)
10 pF Input Capacitance