ON FDC6321C

MOSFET（金属氧化物）逻辑电平门N 和 P 沟道25V680mA，460mA450 毫欧 @ 500mA，4.5V1.5V @ 250µA

Overview

These dual N & P Channel logic level enhancement mode field effect transistors are produced using a proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for digital transistors in load switching applications. Since bias resistors are not required this dual digital FET can replace several digital transistors with different bias resistors.

Features

? N?Channel 0.68 A, 25 V

RDS(ON) = 0.45  @ VGS = 4.5 V

? P?Channel ?0.46 A, ?25 V

RDS(ON) = 1.1  @ VGS = ?4.5 V

? Very Low Level Gate Drive Requirements Allowing Direct

Operation in 3 V Circuits. VGS(th) < 1.0 V.

? Gate?Source Zener for ESD Ruggedness. >6 kV Human Body Model

? Replace Multiple Dual NPN & PNP Digital Transistors

? This is a Pb?Free Device

Applications

low voltage applications