Altera EPM9560ARC208-10N

系统内可编程10 ns35560153

Overview

The MAX 9000 family of in-system-programmable, high-density, highperformance EPLDs is based on Altera’s third-generation MAX architecture. Fabricated on an advanced CMOS technology, the EEPROMbased MAX 9000 family provides 6,000 to 12,000 usable gates, pin-to-pin delays as fast as 10 ns, and counter speeds of up to 144 MHz.

Features

MAX® 9000A Series
208-BFQFP Exposed Pad package
153 I/Os
The operating temperature of 0°C~70°C TA

Surface Mount Mounting Type

Applications

There are a lot of Intel
EPM9560ARC208-10N CPLDs applications.

• Power up sequencing
• Voltage level translation
• Timing control
• Interface bridging
• I/O expansion
• Discrete logic functions
• Bootloaders for FPGAs
• Address decoders
• Custom state machines
• Digital systems