Xilinx XC95216-10PQ160I

系统内可编程（最少 10000 次编程/擦除循环）10 ns12216133

Overview

Description The XC95216-10PQ160I is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of eight 36V18 Function Blocks, providing 4,800 usable gates with propagation delays of 10 ns. See Figure 2 for the architecture overview. Features • 10 ns pin-to-pin logic delays on all pins • fCNT to 111 MHz • 216 macrocells with 4,800 usable gates • Up to 166 user I/O pins • 5V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range • Enhanced pin-locking architecture • Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals • Extensive IEEE Std 1149.1 boundary-scan (JTAG) support • Programmable power reduction mode in each macrocell • Slew rate control on individual outputs • User programmable ground pin capability • Extended pattern security features for design protection • High-drive 24 mA outputs • 3.3V or 5V I/O capability • Advanced CMOS 5V FastFLASH™ technology • Supports parallel programming of more than one XC9500 concurrently • Available 160-pin PQFP, 352-pin BGA, and 208-pin HQFP packages (Note: 352-pin BGA packages are being discontinued for this device)

Features

XC9500 Series
160-BQFP package
133 I/Os
The operating temperature of -40°C~85°C TA
160 pin count
160 pins
3.3/55V power supplies

Surface Mount Mounting Type

Applications

There are a lot of Xilinx Inc.
XC95216-10PQ160I CPLDs applications.

• Custom state machines
• Digital systems
• Portable digital devices
• Handheld digital devices
• Battery operated portable devices
• Complex programmable logic devices
• Digital designs
• Field programmable gate
• Address decoding
• D/T registers and latches