ST STM32G473VBT6

ARM® Cortex®-M4170MHz128KB（128K x 8）

Overview

The STM32G473xB/xC/xE devices are based on the high-performance Arm® Cortex®-M4 32-bit RISC core. They operate at a frequency of up to 170 MHz.

The Cortex-M4 core features a single-precision floating-point unit (FPU), which supports all the Arm single-precision data-processing instructions and all the data types. It also implements a full set of DSP (digital signal processing) instructions and a memory protection unit (MPU) which enhances the application’s security. These devices embed high-speed memories (512 Kbytes of Flash memory, and 128 Kbytes of SRAM), a flexible external memory controller (FSMC) for static memories (for devices with packages of 100 pins and more), a Quad SPI Flash memory interface, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix. The devices also embed several protection mechanisms for embedded Flash memory and SRAM: readout protection, write protection, securable memory area and proprietary code readout protection. The devices embed peripherals allowing mathematical/arithmetic function acceleration (CORDIC for trigonometric functions and FMAC unit for filter functions). They offer five fast 12-bit ADCs (5 Msps), seven comparators, six operational amplifiers, seven DAC channels (3 external and 4 internal), an internal voltage reference buffer, a low-power RTC, twothree general-purpose 32-bit timers, three 16-bit PWM timers dedicated to motor control, seven general-purpose 16-bit timers, and one 16-bit low-power timer. They also feature standard and advanced communication interfaces such as:

Features

Includes ST state-of-the-art patented

technology

? Core: Arm? 32-bit Cortex?-M4 CPU with FPU,

Adaptive real-time accelerator (ART

Accelerator) allowing 0-wait-state execution

from Flash memory, frequency up to 170 MHz

with 213 DMIPS, MPU, DSP instructions

? Operating conditions:

– VDD, VDDA voltage range:

1.71 V to 3.6 V

? Mathematical hardware accelerators

– CORDIC for trigonometric functions

acceleration

– FMAC: filter mathematical accelerator

? Memories

– 512 Kbytes of Flash memory with ECC

support, two banks read-while-write,

proprietary code readout protection

(PCROP), securable memory area, 1 Kbyte

OTP

– 96 Kbytes of SRAM, with hardware parity

check implemented on the first 32 Kbytes

– Routine booster: 32 Kbytes of SRAM on

instruction and data bus, with hardware

parity check (CCM SRAM)

– External memory interface for static

memories FSMC supporting SRAM,

PSRAM, NOR and NAND memories

– Quad-SPI memory interface

? Reset and supply management

– Power-on/power-down reset

(POR/PDR/BOR)

– Programmable voltage detector (PVD)

– Low-power modes: sleep, stop, standby

and shutdown

– VBAT supply for RTC and backup registers

Applications

static memory