NXP Semiconductors 74LV74PW,118

117ns @ 5V，50pF1V ~ 5.5V

Overview

The 74LV74PW is a dual positive-edge trigger D-type Flip-flop with set and reset. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD\) and (nRD\) inputs and complementary nQ and nQ\ outputs. The set and reset are asynchronous active low inputs that operate independently of the clock input. Information on the data input is transferred to the nQ output on the low-to-high transition of the clock pulse. The nD inputs must be stable one set-up time prior to the low-to-high clock transition, for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

Features

74LV Series
Bulk Package
Set(Preset) and Reset Function
Complementary Output Type
2 Number of Elements
1 Number of Bits per Element
110 MHz Clock Frequency
17ns @ 5V, 50pF Max Propagation Delay @ V, Max CL
Positive Edge Trigger Type
12mA, 12mA Current - Output High, Low
1V ~ 5.5V Voltage - Supply
Surface Mount Mounting Type
80 µA Current - Quiescent (Iq)
3.5 pF Input Capacitance