Micron MT41J64M16TW-093:J

64M x 160°C ~ 95°C（TC）

Overview

DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clockcycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, onehalf-clock-cycle data transfers at the I/O pins. The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. 

• Self refresh temperature (SRT)

Features

Tray Package
Volatile Memory Type
DRAM Memory Format
1Gbit Memory Size
64M x 16 Memory Organization
Parallel Memory Interface
1.066 GHz Clock Frequency
1.425V ~ 1.575V Voltage - Supply
0°C ~ 95°C (TC) Operating Temperature
Surface Mount Mounting Type