Lattice GAL20V8Z-12QJ

EE PLD8

Overview

The GAL20V8Z-12QJ , at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Eras-able(E2) floating gate technology to provide the highest speed performance available in the PLD market High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. An important subset of the many architecture configura-tions possible with the GAL20V8  are the PAL architectures listed in the table of the macrocell description section. GAL20V8Z-12QJ devices are capable of emulating any of these PAL architectures with full function/fuse map/parametric compatibility. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition,100 erase/write cycles and data retention in excess of 20 years are specified.

— Standard Logic Speed Upgrade

Features

GAL20V8Z Series
Bulk Package
EE PLD Programmable Type
8 Number of Macrocells
Surface Mount Mounting Type