Lattice GAL16V8D-7LP

EE PLD8

Overview

The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently.

— Standard Logic Speed Upgrade

Features

GAL®16V8 Series
20-DIP (0.300, 7.62mm) package
8 I/Os
The operating temperature of 0°C~75°C TA
20 pin count
20 pins
5V power supplies
8 outputs

Through Hole Mounting Type

Applications

There are a lot of Lattice Semiconductor Corporation
GAL16V8D-7LP CPLDs applications.

• I/O expansion
• Discrete logic functions
• Bootloaders for FPGAs
• Address decoders
• Custom state machines
• Digital systems
• Portable digital devices
• Handheld digital devices
• Battery operated portable devices
• Complex programmable logic devices