IDT 71V546S133PFI

128K x 364.2 ns-40°C ~ 85°C（TA）

Overview

The 71V546S133PFG 3.3V CMOS SRAM is organized as 128K x 36 bits. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turn-around. The 71V546S133PFG contains data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.

Features

Bulk Package
Volatile Memory Type
SRAM Memory Format
4.5Mbit Memory Size
128K x 36 Memory Organization
Parallel Memory Interface
133 MHz Clock Frequency
4.2 ns Access Time
3.135V ~ 3.465V Voltage - Supply
Surface Mount Mounting Type