AMD XCR3128XL-10VQG100I

系统内可编程（最少 1K 次编程/擦除循环）9.1 ns812884

Overview

The CoolRunner XPLA3 (eXtended Programmable Logic Array) family of CPLDs is targeted for low power systems that include portable, handheld, and power sensitive applications. Each member of the CoolRunner XPLA3 family includes Fast Zero Power (FZP) design technology that combines low power and high speed. With this design technique, the CoolRunner XPLA3 family offers true pin-to-pin speeds of 5.0 ns, while simultaneously delivering power that is less than 56 μW at standby without the need for "turbo bits" or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any other CPLD. CoolRunner devices are the only TotalCMOS PLDs, as they use both a CMOS process technology and the patented full CMOS FZP design technique. The FZP design technique combines fast nonvolatile memory cells with ultra-low power SRAM shadow memory to deliver the industry’s lowest power 3.3V CPLD family.

The CoolRunner XPLA3 family features also include the industry-standard, IEEE 1149.1, JTAG interface through which boundary-scan testing, In-System Programming (ISP), and reprogramming of the device can occur. The CoolRunner XPLA3 CPLD is electrically reprogrammable using industry standard device programmers.

Features

CoolRunner XPLA3 Series
100-TQFP package
84 I/Os
The operating temperature of -40°C~85°C TA
100 pin count
100 pins

Surface Mount Mounting Type

Applications

There are a lot of Xilinx Inc.
XCR3128XL-10VQG100I CPLDs applications.

• Digital systems
• Portable digital devices
• Handheld digital devices
• Battery operated portable devices
• Complex programmable logic devices
• Digital designs
• Field programmable gate
• Address decoding
• D/T registers and latches
• Synchronous or asynchronous mode