ADI HMC988LP3E

是CML，CMOS，LVDS，LVPECLLVPECL

Overview

The HMC988LP3E is a an ultra low noise clock divider capable of dividing by 1/2/4/8/16/32. It is a versatile device with additional functionality including adjustable output phase, adjustable delay in 60 steps of ~ 20 ps, a clock synchronization function, and a clock invert option. Housed in a compact 3x3 mm SMT QFN package, the clock divider offers a high level of functionality. The device works with 3.3V supply or may be connected to 5V supply and utilize the optional on-chip regulator. This on-chip regulator may be bypassed. Up to 8 addressable HMC988LP3E devices can be used together on the SPI bus. The HMC988LP3E is ideally suited for data converter applications with extremely low phase noise requirements.

Features

Strip Package
Available in the 16-VFQFN Exposed Pad
Supply voltage of 3.3V
Operating supply voltage of 4.5V

Surface Mount Mounting Type

Applications

There are a lot of Analog Devices Inc.
HMC988LP3E Clock Generators applications.

• Instrument
• Automatic test equipment
• Wide area power system
• Digital circuits
• Wireless base station for LTE, LTE-advanced
• Picocells, femtocells and small cells
• Sampling clocks for ADC and DAC
• 1 Gigabit Ethernet
• 10 Gigabit Ethernet
• FPGA and processor clocks