ADI AD9642BCPZ-250

14250M1差分1.7V ~ 1.9V1.7V ~ 1.9V-40°C ~ 85°C

Overview

The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth inputs that can support a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) is provided to compensate for variations in the ADC clock duty cycle, allowing the converter to maintain excellent performance.

The AD9642 is available in a 32-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent.

Features

Maximum Clock Output Frequency: 3255 MHz

Multi-Mode: Dual PLL, Single PLL, and Clock Distribution

1-1023 CLKout Divider

1-8191 SYSREF Divider

25-ps Step Analog Delay for SYSREF Clocks

Digital Delay and Dynamic Digital Delay for Device Clock and SYSREF

Applications

Test and Measurement

RADAR

Microwave Backhaul

Data Converter Clocking