ADI AD9500BP

时钟发生器无ECL，TTLECL

Overview

The AD9500BP is a digitally programmable delay generator, which provides programmed delays, selected through an 8-bit digital code, in resolutions as small as 10 ps. The AD9500BP is constructed in a high performance bipolar process, designed to provide high speed operation for both digital and analog circuits. The AD9500BP employs differential TRIGGER and RESET inputs which are designed primarily for ECL signal levels but function with analog and TTL input levels. An onboard ECL reference midpoint allows both of the inputs to be driven by either single ended or differential ECL circuits. The AD9500BP output is a complementary ECL stage, which also provides a QR parallel output circuit to facilitate reset timing implementations. The digital control data is passed to the AD9500BP through a transparent latch controlled by the LATCH ENABLE signal. In the transparent mode, the internal DAC of the AD9500BP will attempt to follow changes at the inputs. The LATCH ENABLE is otherwise used to strobe the digital data into the AD9500BP latches.

  10 ps Delay Resolution   2.5 ns to 10 ms Full-Scale Range   Fully Differential Inputs   Separate Trigger and Reset Inputs   Low Power Dissipation—310 mW   MIL-STD-883 Compliant Versions Available

Features

AD9500 Series
Bulk Package
Clock Generator Type
No PLL
ECL, TTL Input
ECL Output
1 Number of Circuits
10:2 Ratio - Input:Output
No/Yes Differential - Input:Output
No/No Divider/Multiplier
Surface Mount Mounting Type